The present application is generally related to the fields of memory cell sensing and analog to digital converters and, more particularly to an apparatus and method for enhancing the resolution of an analog to digital converter and/or enhancing memory cell sensing.
U.S. Pat. No. 4,998,109 is one example of a prior art technique that utilizes a delay line for purposes of enhancing the resolution of an analog to digital converter beyond the limitation that is imposed through the use of a given clock or reference frequency. That is, the resolution is increased to a value that is greater than the resolution that would otherwise be provided through the use of the given clock frequency alone. Applicant recognizes, however, that the use of such a prior art technique is problematic under certain circumstances that can take place during the operation of the analog to digital converter, as will be described in detail below.
The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.